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| 74VHC112 Dual J-K Flip-Flops with Preset and Clear September 1995 Revised April 1999 74VHC112 Dual J-K Flip-Flops with Preset and Clear General Description The VHC112 is an advanced high speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. The LOW signal on PR or CLR prevents clocking and forces Q and Q HIGH, respectively. Simultaneous LOW signals on PR and CLR force both Q and Q HIGH. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Features s High speed: fMAX = 200 MHz (typ) at VCC = 5.0V s Low power dissipation: ICC = 2 A (max) at TA = 25C s High noise immunity: VNIH = VNIL = 28% VCC (min) s Power down protection is provided on all inputs s Pin and function compatible with 74HC112 Ordering Code: Order Number 74VHC112M 74VHC112SJ 74VHC112MTC 74VHC112N Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Pin Descriptions Pin Names J1, J2, K1, K2 CLK1, CLK2 CLR1, CLR2 PR1, PR2 Q1, Q2, Q1, Q2 Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active LOW) Direct Preset Inputs (Active LOW) Outputs Description (c) 1999 Fairchild Semiconductor Corporation DS012123.prf www.fairchildsemi.com 74VHC112 Truth Table Inputs PR L H L H H H H CLR H L L H H H H CP X X J X X X h l h l K X X X h h l l Outputs Q H L H Q0 L H Q0 Q L H H Q0 H L Q0 X H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial = HIGH-to-LOW Clock Transition Q0 (Q0) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram (One Half Shown) www.fairchildsemi.com 2 74VHC112 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT ) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260C -0.5V to +7.0V -0.5V to +7.0V -0.5V to VCC + 0.5V -20 mA 20 mA 25 mA 50 mA -65C to +150C Recommended Operating Conditions (Note 2) Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC = 3.3V 0.3V VCC = 5.0V 0.5V 0 100 ns/V 0 20 ns/V 2.0V to +5.5V 0V to +5.5V 0V to VCC -40C to +85C Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0 - 5.5 2.0 3.0 - 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IIN ICC Input Leakage Current Quiescent Supply Current 0 - 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 2.0 2.0 3.0 4.5 TA = 25C Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 1.0 20.0 V A A IOL = 4 mA IOL = 8 mA V IN = 5.5V or GND V IN = VCC or GND V V IOH = -4 mA IOH = -8 mA VIN = VIH IOL = 50 A or VIL V Typ Max TA = -40C to +85C Min 1.50 0.7 VCC 0.50 0.3 VCC Max Units V V VIN = VIH IOH = -50 A or VIL Conditions 3 www.fairchildsemi.com 74VHC112 AC Electrical Characteristics Symbol fMAX Parameter Maximum Clock Frequency 5.0 0.5 tPLH tPHL Propagation Delay Time (CP to Qn or Qn) 5.0 0.5 tPLH tPHL Propagation Delay Time (PR or CLR to Qn or Qn) 5.0 0.5 CIN CPD Input Capacitance Power Dissipation Capacitance Note 3: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC/4 (per F/F), and the total CPD when n pcs of the Flip-Flop operate can be calculated by the following equation: CPD (total) = 30 + 14 * n VCC (V) 3.3 0.3 TA = 25C Min 110 90 150 120 Typ 150 120 200 185 8.5 10.0 5.1 6.3 6.7 9.7 4.6 6.4 4 18 11.0 15.0 7.3 10.5 10.2 13.5 6.7 9.5 10 Max TA = -40C to +85C Min 100 80 135 110 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 13.4 16.5 8.8 12.0 11.7 15.0 8.0 11.0 10 Max Units MHz MHz ns ns ns ns pF pF Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF VCC = Open (Note 3) 3.3 0.3 3.3 0.3 AC Operating Requirements Symbol tW tS tH tREC Minimum Pulse Width (CP or CLR or PR) Minimum Setup Time (Jn or Kn to CPn) Minimum Hold Time (Jn or Kn to CPn) Minimum Recovery Time (CLR or PR to CP) Note 4: VCC is 3.3 0.3V or 5.0 0.5V Parameter VCC (Note 4) (V) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 TA = 25C Typ TA = -40C to +85C Guaranteed Minimum 5.0 5.0 5.0 4.0 1.0 1.0 6.0 5.0 5.0 5.0 5.0 4.0 1.0 1.0 6.0 5.0 Units ns ns ns ns www.fairchildsemi.com 4 74VHC112 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com 74VHC112 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 6 74VHC112 Dual J-K Flip-Flops with Preset and Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. |
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